1. Field of the Invention
The present invention relates generally to the field of integrated circuit fabrication and, more particularly, to a silicon buried digit line (BDL) access device for memories such as DRAM, wherein the buried digit lines are separated with air gaps.
2. Description of the Prior Art
A continuous challenge in the semiconductor memory industry is to decrease the size of memory cell components in order to increase the packing density of the DRAM chips. Over the last few device generations, DRAM manufacturers have developed alternative cell layouts that reduce the area occupied by the memories on chips. The latest designs allow a significant increase in density by burying the address lines or digit lines into the silicon substrate, then fabricating the transistors and capacitors on top to form a vertical stack. Such devices are also known as buried digit line (BDL) access devices.
However, the current BDL technology still has several drawbacks. For example, the BDL access devices have very high digit line-to-digit line (DL-DL) coupling capacitances. The DL-DL capacitance can reach up to 25%-30% of the total digit line capacitance using current metal Digit line schemes. The high percentage of DL-DL coupling causes significant sense margin loss even though the total digit line capacitance may be lower than in other technologies. For the available sense amp schemes to work, the DL-DL capacitance should not exceed 20% of the total DL capacitance, and even preferably represent less than 10% of the total capacitance. Hence, it is desired to provide an improved BDL device for DRAM applications that is capable of reducing the DL-DL coupling percentage of the total DL capacitance.